`timescale 1ns / 1ps

////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:   14:02:54 12/07/2011
// Design Name:   FiltrDA
// Module Name:   C:/11/Filtr_DA/Filtr_DA/Filtr_DA_testbench.v
// Project Name:  Filtr_DA
// Target Device:  
// Tool versions:  
// Description: 
//
// Verilog Test Fixture created by ISE for module: FiltrDA
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////

module Filtr_DA_testbench;

	// Inputs
	reg [7:0] signal;
	reg clk;
	reg reset;

	// Outputs
	wire [8:0] filtered_sig;

	// Instantiate the Unit Under Test (UUT)
	filtrDA uut (
		.signal(signal), 
		.filtered_sig(filtered_sig), 
		.clk(clk), 
		.reset(reset)
	);

	initial begin
		// Initialize Inputs
		signal = 0;
		clk = 1;
		reset = 1;


		// Wait 100 ns for global reset to finish
		#8;
		reset = 0;
		signal = -8'sd100;
		#8;
		signal = 0;
		#160;
      $finish;
	end	
		
		always begin
			#4 clk=0;
			#4 clk=1;		
		end
      
      
endmodule

